A fundamental problem in switched networks is the “charge injection” problem when switched elements utilizing metal-oxide-semiconductor (MOS) in a circuit network are switched off. Such a problem is described in Je-Hurn, Shieh, Mahesh Patil, Bing J. Sheu, “Measurement and Analysis of Charge Injection in MOS Analog Switches”, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 2, pp. 277-281, April 1987; George Wegmann, Eric A. Vittoz, Fouad Rahali, “Charge Injection in Analog MOS Switches”. IEEE Journal of Solid-State Circuits, Vol SC-22, No. 6, pp. 1091-1097, December 1987. Redundant charges are injected into nodes, particularly for high impedance nodes, causing an erroneous voltage to appear at the circuit output. This erroneous voltage can be very large when amplified. These redundant charges typically result from two types of injection mechanisms. A first mechanism is caused by charges stored in MOS transistors when the channel is conducting (transistor is switched on). When switching off the transistor, the stored charges are forced to flow out of the channel, introducing redundant charges into the corresponding connecting nodes. A second mechanism, called a clock feed-through error, results from a clocking signal coupled to the connecting node via parasitic capacitors residing in the MOS transistor.
FIG. 1 illustrates a single N-channel enhancement mode MOS transistor (NMOS) switch in the prior art. In FIG. 1, an input signal to be switched is applied to the drain (D) terminal. The clock signal T is applied to the gate (G) terminal. The output signal is then available at the source (S) terminal when the switch is conducting (when clock T is high). In the following descriptions of switch configurations, the term “source” and “drain” are interchangeable, since the MOS transistor is a bilaterally symmetrical device. A terminal functions as a source or drain depending on the relative potential of the two terminals. If the N-channel transistor is formed in a N-substrate, a P-well is connected to the bulk terminal. Conversely, if the N-channel device is formed in a P-substrate, the P-substrate itself connects to the bulk. It is standard practice to connect all the P-wells in a N-substrate CMOS integrated circuit to the lowest voltage in the circuit. Hence, the bulk terminal will connect to ground or Vss. During the conduction of the NMOS switch, charges are stored in the conducting channel. When the switch is turned off (when clock T is low), the previously stored charges are forced to flow out to both sides of the source and drain terminals. The amount of charges injected depends on the impedance of each terminal. In addition, this single switch configuration is also subjected to clock feed-through error.
FIG. 2 shows a complementary MOS (CMOS) switch comprised of a NMOS having its source (S) and drain (D) connected in parallel to the source and drain of a P-channel MOS (PMOS) in the prior art. Clock signals T1 and T2, applied to the respective gate (G) terminals, are out of phase with each other. Hence, when the switch is on, both transistors will be conducting at the same time. The advantage of using a CMOS switch is that the effect of charge injection in a NMOS transistor is cancelled by the corresponding charge injection in a PMOS transistor when both devices turn off, provided the transistor is the same size. In practice, however, the net charge cancellation is difficult to achieve without additional clocking circuitry and a corresponding decrease in operating speed. If both transistors do not turn off at exactly the same time, the charge injected by the transistor turning off first will be swept through the transistor, which is still on, resulting in contribution of net charge injection. Furthermore, channel charge of a MOS device is a function of its threshold voltage as well as its size. It is well known that N-channel thresholds cannot be precisely the same absolute value as P-channel thresholds on a typical process. Hence, even the presence of opposite transition of clocking signals on a NMOS and a PMOS results in the parasitic capacitances on each transistor being different. Therefore, clock feed-through errors cannot be cancelled effectively.
A more effective method is to utilize dummy switches as illustrated in FIG. 3. Exemplary dummy switching techniques can be found in Christoph Erichenberger, Walter Guggenbuhl, “Dummy Transistor Compensation of Analog MOS Switches”, IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, pp. 1143-1145, August 1989; Christoph Erichenberger, Walter Guggenbuhl, “On Charge Injection in Analog MOS Switches and Dummy Switch Compensation Techniques”, IEEE Transactions on Circuits and Systems, Vol. 37, No. 2, pp. 256-264, February 1990. The overall switch element consists of a main transistor switch (MM) and a dummy transistor switch (MD). The size of the dummy transistor switch is about half of the main transistor switch. The drain (D) and the source (S) terminals of the dummy transistor are shorted together and in turn connected to the source (S) of main transistor. The drain of the main transistor will form the other signal terminal of the switch element. Clock signals T1 and T2, applied to the respective gate (G) terminals, are out of phase with each other. Hence, only one transistor is switched on at a time. The terminal where the dummy transistor resided will connect to the high impedance node of the circuit where the charge injection problem will occur, while the other signal terminal will connect to the low impedance node. When the main transistor is turned off, the dummy transistor is turned on, hence the previously stored charges in the main transistor switch are absorbed by the turning on of the dummy transistor. The “half-sized” dummy transistor technique assumed that half of the stored charges would be forced out on both sides of signal terminals from the main transistor. In practice, if the terminal impedances are unbalanced, the charge distribution will not be equal, resulting in some charges injected to the high impedance node. In addition, clock feed-through error will still prevail since the parasitic capacitances of the main and dummy transistors are different. Furthermore, matching the main and dummy transistors is not as good as matching two same-sized transistors.
FIG. 4 shows a schematic diagram of a charge injection compensating circuit in the prior art. Wei-Chen Shen, Yen-Bin Gu, Chu-Chang Lin, Min-Jer Chen, Po-Chin Hsu, Tien-Yu Wu, “Compensating Circuit for MOSFET Analog Switches”, U.S. Pat. No. 5,479,121, Dec. 26, 1995 describes such a circuit. The circuit comprises a NMOS transistor switch M2 being connected in parallel to a capacitor C3. The drain of M2 is connected to capacitor C1, which is in series with C2. The source of M2 is connected to the other terminal of C2 which is connected to the gates of the CMOS inverting amplifier M3 and M4 at node B. The output of the CMOS inverting amplifier is connected back to the drain of M2. The gate of M2 is connected to the switching clock together with the gate of the main NMOS transistor switch M1, whose drain is connected to the incoming signal. The source of M1 will form a node in between C1 and C2 at node A. Capacitors C1, C2 and C3 each have a capacitance of at least 0.2 pF, and the inverting amplifier has a gain of at least 30 dB. Since the gain of the CMOS inverting amplifier is significantly greater, the parasitic capacitance has no effect on the error compensating characteristics of the compensating circuit. In operation, the node A is connected at the point in the circuit being compensated where the turn off charge causing the error is injected. There is a turn off charge from M2, Q2, injected into node B and another turn off charge from M1, Q1, into node A. The voltage at node A due to these charges is proportional to Q2 multiplied by the capacitance C1 subtracted from Q1 multiplied by the capacitance C3. By properly choosing the values of C1 and C3, the voltage at the node A due to turn off charges can be made zero or nearly zero. Often Q1 and Q2 are equal so that C1 and C3 are chosen to be equal. However, this compensation circuit still suffers from clock feed-through error because the clocking of the main and compensation switches are coming from the clock. Moreover, as the compensation circuit consists of many components and an amplifier, it will occupy much larger area and higher power consumption as compared to the previous three prior arts.